The present invention generally relates to a method for forming an electrical conductor in an electronic structure and more particularly, relates to a method for forming interconnects in a semiconductor structure and structures formed.
The technology of making metal conductors to provide for vias, lines and other recesses in semiconductor chip structures, flat panel displays and package applications has been developed in the past decade. For instance, in developing interconnection technology for very-large-scale-integrated (VLSI) structures, aluminum has been utilized as the primary metal source for contacts and interconnects in semiconductor regions or devices located on a single substrate. Aluminum has been the material of choice because of its low cost, good ohmic contact and high conductivity. However, pure aluminum thin-film conductors have undesirable properties such as a low melting point which limits its use to low temperature processing and possible diffusion into the silicon during annealing which leads to contact and junction failure, and poor electromigration resistance. Consequently, a number of aluminum alloys have been developed which provided advances over pure aluminum.
Recently developed ULSI technology has placed more stringent demands on the wiring requirements due to the extremely high circuit densities and faster operating speeds required of such devices. This leads to higher current densities in increasingly smaller conductor lines. As a result, higher conductance wiring is desired which requires either larger cross-section wires for aluminum alloy conductors or a different wiring material that has a higher conductance. The obvious choice in the industry is to develop the latter which includes pure copper for its desirable high conductivity.
In the formation of ULSI interconnection structures such as vias and lines, copper can be deposited into such recesses to interconnect semiconductor regions or devices located on the same substrate. However, copper is known to have problems in semiconductor devices. The electromigration phenomenon occurs when the superposition of an electric field onto random thermal diffusion in a metallic solid causes a net drift of atoms in the direction of electron flow. This can lead to degradation in interconnect reliability. Diffusion of copper atoms into the silicon substrate or ILD can also cause device failure and poor reliability. In addition, pure copper does not adhere well to oxygen-containing dielectrics such as silicon dioxide and polyimide. To fully utilize copper in interconnection technology, the adhesion, diffusion and electromigration properties of copper must be improved control.
A schematic of an enlarged, cross-sectional view of an electronic structure that utilizes conventional interconnections made of a copper or copper alloys is shown in FIG. 1. The electronic structure 10 contains two levels of copper interconnections 12, 16 and one stud level 14 illustrating a copper wiring structure formed in a Damascene process on a pre-fabricated device 20. The device 20 is built on a semi-conducting substrate 24. As shown in FIG. 1, a typical Damascene level is first fabricated by the deposition of an ILD stack 26. The ILD stack 26 is then patterned and etched using standard lithograph and dry etch techniques to produce a desired wiring or via pattern. The process is then followed by the metal depositions of a thin adhesion/diffusion barrier liner 18 and copper or copper alloy metallurgy 12 wherein a bottom capping layer such as silicon nitride layer 28 is used as a diffusion barrier/etch stop which is previously deposited on top of the device 20 to protect against copper diffusion. After the copper or copper alloy interconnection 12 is formed, a top cap layer such as a silicon nitride layer 32 is deposited and used as an etch stop layer for defining the next level copper interconnection 14. After a second level ILD stack 34 is deposited, a recess for an interconnect is etched into the ILD stack 34 and the silicon nitride layer 32.
An interlevel copper alloy stud 14 with liner 22 is then deposited by a technique similar to that used in depositing the first level copper or copper alloy interconnection 12. A variety of metal deposition techniques can be used for filling the trench or via. These techniques include a collimated sputtering process, an ionized sputtering process, a hollow cathode magnetron sputtering process, a chemical vapor deposition process, an electroless plating process and an electrolytic plating process. Other techniques such as a co-deposition method in which copper and an alloying element are co-deposited can also be used in forming the copper alloys. For instance, the co-deposition methods include co-sputtering, xe2x80x9calloy platingxe2x80x9d, sequential plating of different materials with subsequent annealing, chemical vapor deposition, sequential chemical vapor deposition and co-evaporation. After the completion of the interlevel copper alloy stud 14, another similar process is repeated to form the second level copper interconnection 16 with liner 24 in a third ILD stack layer 38. An etch stop layer 36 such as silicon nitride is utilized between the stud and the second level interconnections. Finally, a top capping layer 42 is deposited on top of the copper wiring structure 10 for protecting the device from the environment.
More recently, void-free and seamless conductors are produced by electroplating copper from plating baths that contain additives. The capability of the electroplating method to superfill structural features without leaving voids or seams is unique and superior to that of other deposition techniques. Electrolytic copper plating techniques used in damascene structures can be defect-free if the deposited seed layer is continuous and has a uniform thickness even in the deepest area of the structural feature to be plated. The copper seed layer is typically deposited by a physical vapor deposition technique or other techniques over a barrier layer that prevents diffusion of copper into the insulator such as Ta, TaN, TiN or TaSiN. When the deposited seed layer is too thin at the bottom or near-bottom walls of a structural feature, plating does not occur and a void is created.
In order to eliminate the non-continuous deposition problem occurring during sputtering of a copper seed layer, a seed layer of a larger thickness is normally deposited. The deposition of a thick seed layer helps to eliminate the plated Cu voiding problem, however, it creates another one of equal or even greater significance, i.e. poor electromigration resistance in the resultant structure. The poor electromigration resistance of the structure is caused by the fact that the seed layer itself has weak electromigration resistance when compared to the much higher electromigration resistance of the plated film. It is also noted that in future generations of chips, the seed layer will contribute an increasing part of the total structure based on the decreasing dimensions of the features and the inability to decrease the thickness of the seed layer proportionally for reason stated above as well as the thickness uniformity requirements in electrolytic plating.
The Cu damascene process consists of the formation of trenches and vias in a dielectric material (such as SiO2), which stops at an etch-stop shown as layer 46 in FIG. 2 filling the vias and trenches with a metal stack containing a barrier layer followed by Cu and then removing the excess metal from the field region typically by chemical/mechanical polishing. This is shown in FIGS. 2A and 2B, for a single damascene structure 50 and a dual damascene structure 40, respectively. When Cu damascene interconnects are produced using plated Cu, typically a physical vapor deposition Cu film 26 (seed layer) is deposited on the barrier layer to improve the substrate conductivity and to allow for uniform Cu plating. The as-plated Cu 44 is fine grained (0.05-0.2 xcexcm grain size) but at room temperature over time, the Cu grains will grow to about 1xcx9c5 xcexcm in size.
It is desirable for the interconnect microstructure to be large grained for electromigration and stress voiding purposes because grain boundary diffusion is minimized. Since the room temperature grain growth can occur over a time period of 1-4 days and is dependent on plated film thickness and impurity content, it is not practical to wait for room temperature grain growth prior to further processing. Therefore, a typical plated Cu damascene process requires that plated Cu be annealed post-plating but prior to chemical mechanical polishing (CMP) to allow grain growth to occur within 30xcx9c60 min. It has been shown that interconnects formed with a post-plate anneal have a higher incidence of stress voids than interconnects formed with a room temperature anneal. If the microstructure of the as-plated film is large grained, the anneal step would not be required.
It is therefore an object of the present invention to provide a method for forming interconnects in a semiconductor structure that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for forming copper interconnects with large grains for improved electromigration and stress voiding proportions.
It is a further object of the present invention to provide a method for forming copper interconnects that have a bamboo or near bamboo microstructure.
It is another further object of the present invention to provide a method for forming copper interconnects of large grains by first forming a copper seed layer of large grains in the interconnect opening.
It is still another object of the present invention to provide a method for forming copper interconnects in a semiconductor structure by first depositing a copper seed layer in the interconnect opening and then annealing the copper seed layer until the grains are increased in size by at least 1.5 times.
It is still another further object of the present invention to provide a semiconductor structure that has at least one copper interconnect created by forming a seed layer such that the grain size of the filler layer is maximized.
It is yet another further object of the present invention to provide a semiconductor structure that has at least one copper interconnect formed therein by a copper seed layer having a thickness of 0.0005-0.50 xcexcm and a copper filler layer having a grain size at least the thickness of the seed layer.
In accordance with the present invention, a method for forming copper interconnect in a semiconductor structure that has large copper grains and the structures formed are disclosed.
In a preferred embodiment, a method for forming metal interconnects in a semiconductor structure can be carried out by the operating steps of first providing a semiconductor structure that has an interconnect opening formed therein, depositing a seed layer of a first metal that has an average grain size between 0.0005-0.50 xcexcm in the interconnect opening, heating the semiconductor structure to a temperature sufficient to grow the average grain size of the seed layer by at least a factor of 1.5 times and depositing a filler layer of a second metal in the interconnect opening overlaying the seed layer such that the filler layer of the second metal has a final average grain size comparable to the average grain size of the seed layer.
The method for forming metal interconnects in a semiconductor structure may further include the step of depositing the filler layer of a second metal that is the same as the first metal in the seed layer, or the step of depositing the seed layer and the filler layer in Cu. The method may further include the steps of depositing the filler layer in Au and depositing the seed layer in Au or Pt, or the steps of depositing the filler layer in Cu and depositing the seed layer in Pt, or the steps of depositing the filler layer in Ni and depositing the seed layer in Ni. The method may further include the step of heating the seed layer prior to depositing the filler layer to a temperature between about 50xc2x0 C. and about 500xc2x0 C., or preferably to a temperature between about 300xc2x0 C. and about 400xc2x0 C. when the first metal is Cu, or the step of heating the semiconductor structure to a temperature between about 50xc2x0 C. and about 500xc2x0 C. in a reducing atmosphere of forming gas or in an inert gas. The method may further include the step of heating the semiconductor structure for a time period of less than two hrs, or preferably between about xc2xd hrxcx9c1 hr in a furnace or 1 secxcx9c100 sec in a RTA (rapid thermal annealing) when the first metal is Cu. The method may further include the step of depositing the seed layer to a thickness between above 0.0005 xcexcm and about 0.5 xcexcm.
The present invention is further directed to a semiconductor structure that includes an insulating material layer on a top surface of the semi-conductor structure, an interconnect opening in the insulating material layer, a diffusion barrier layer in the interconnect opening, a seed layer of a first metal on top of the diffusion barrier layer, the seed layer is formed of grains that have an average grain size of 0.0005-0.50 xcexcm, and a filler layer of a second metal filling the interconnect opening formed of grains that have an average grain size at least 50% of the average grain size of the seed layer.
In the semiconductor structure, the diffusion barrier layer may be formed of refractory metal or refractory metal nitride. The first metal and the second metal may be of the same material. For example, first metal and the second metal are both Cu. The average grain size of the filler layer is at least 50% of the average grain size of the seed layer. The first metal may be Au or Pt, and the second metal may be Au. The first metal may be Pt, and the second metal may Cu. The first metal may be Ni, and the second metal may be Ni. The seed layer may have a thickness between about 0.0005 xcexcm and about 0.5 xcexcm, or preferably a thickness between about 0.005 xcexcm and about 0.5 xcexcm, or more preferably a thickness between about 0.05 xcexcm and about 0.25 xcexcm.
In another preferred embodiment, a method for forming a metal interconnect in a semiconductor structure can be carried out by the steps of first providing a semiconductor structure that has an interconnect opening formed therein, then depositing a seed layer of a first metal that has a thickness of at least 0.0005 xcexcm in the interconnect opening, and depositing a filler layer of a second metal in the interconnect opening overlaying the seed layer such that the filler layer of the second metal has an average grain size comparable to the seed layer.
The method for forming an interconnect in a semiconductor structure may further include the step of depositing a diffusion barrier layer in the interconnect opening prior to the deposition step for the seed layer. The method may further include the step of depositing the seed layer and the filler layer of the same metal. For example, the step of depositing the seed layer and the filler layer in Cu. The method may further include the step of depositing the seed layer of Cu to a thickness of at least 0.0005-0.5 xcexcm, or the step of depositing a seed layer of Cu to a thickness of at least 0.0005-0.50 xcexcm such that the filler layer subsequently deposited has an average grain size comparable to the seed. The method may further include the step of depositing the seed layer of copper to a thickness between about 0.0005 xcexcm and about 0.5 xcexcm, or preferably between about 0.05 xcexcm and about 0.25 xcexcm. The method may further include the step of depositing the seed layer of Cu to a thickness between about 0.0005 xcexcm and about 0.5 xcexcm such that a subsequently deposited filler layer has an average grain size comparable to the thickness of the seed layer.
The present invention is further directed to a semiconductor structure that includes a dielectric material layer on top of the semiconductor structure, an interconnect opening in the dielectric material layer, a seed layer of a first metal in the interconnect opening that has a thickness of at least 0.0005-0.5 xcexcm, and a filler layer of a second metal filling the interconnect opening that is formed of grains having an average grain size that is at least the thickness of the seed layer. The filler layer may be formed of grains that have an average grain size that is not larger than five times the thickness of the seed layer, or the filler layer may be formed of grains that have an average grain size comparable to the seed layer thickness. The first metal and the second metal may be Cu. The semiconductor structure may further include a layer of diffusion barrier between the interconnect opening and the seed layer. The first metal may be Au or Pt, while the second metal may be Au. The first metal may be Pt, and the second metal may be Au. The first metal may be Ni, and the second metal may be Ni.